Now showing items 1-2 of 2

  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-07)
    The architecture for an optimistic, highly parallel, scalable, shared memory CPU - the WarpEngine - is described. The WarpEngine CPU allows for parallelism down to the level of single instructions and is tolerant of memory ...
  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-09)
    The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable instructions and memory accesses are time ...

Husam Kinawi has 2 co-authors in Research Commons.