Now showing items 1-5 of 14

  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-07)
    The architecture for an optimistic, highly parallel, scalable, shared memory CPU - the WarpEngine - is described. The WarpEngine CPU allows for parallelism down to the level of single instructions and is tolerant of memory ...
  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-09)
    The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable instructions and memory accesses are time ...
  • Constraints on parallelism beyond 10 instructions per cycle

    Cleary, John G.; Littin, Richard H.; McWha, David J.A.; Pearson, Murray W. (Computer Science, University of Waikato, 1997-11)
    The problem of extracting Instruction Level Parallelism at levels of 10 instructions per clock and higher is considered. Two different architectures which use speculation on memory accesses to achieve this level of performance ...
  • Current techniques for measuring and modeling ATM traffic

    Pearson, Murray W.; Cleary, John G.; Unger, Brian; Williamson, Carey (1996-06)
    ATM has now been widely accepted as the leading contender for the implementation of broadband communications networks (Brinkmann, Lavrijsen, Louis, et al, 1995) ATM networks are no longer restricted to research laboratories, ...
  • Design of a processor to support the teaching of computer systems

    Pearson, Murray W.; Armstrong, Dean Andrew; McGregor, Anthony James (IEEE, 2002)
    Teaching computer systems, including computer architecture, assembly language programming and operating system implementation, is a challenging occupation. At the University of Waikato this is made doubly true because we ...