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A comparison of verilog synthesis frontends

Abstract
A crucial consideration in choosing a frontend synthesis tool is the quality of the synthesised result. This kind of benchmarking is critical to choosing a fit-for-purpose tool. However, to the best of the authors’ knowledge, the only comparison of Odin II, the front-end of Verilog-to-Routing, and another synthesis tool was focused primarily on Odin II and Yosys’ performance with respect to commercial counterparts in the Xilinx ISE tool. Further, such an evaluation is to improve confidence in research findings utilising these tools. The quality of results for a poorly optimised research tool may not reflect the performance of real-world applications, adding uncertainty to any findings and requiring extra work from the researcher to obtain valid results. We compare Odin II and Yosys targeting the Xilinx Artix-7 architecture provided by SymbiFlow.
Type
Conference Contribution
Type of thesis
Series
Citation
Date
2021
Publisher
The International Academy, Research and Industry Association (IARIA)
Degree
Supervisors
Rights
This conference paper has been published online in Think Mind: Proceedings of the Fourteenth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS 2021). Used with permission. © 2021 IARIA.