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dc.contributor.authorCleary, John G.
dc.contributor.authorPearson, Murray W.
dc.contributor.authorKinawi, Husam
dc.date.accessioned2008-10-23T02:51:33Z
dc.date.available2008-10-23T02:51:33Z
dc.date.issued1994-09
dc.identifier.citationCleary, J.G., Pearson, M. & Kinawi, H. (1994). The architecture of an optimistic CPU: the WarpEngine. (Working paper 94/16). Hamilton, New Zealand: University of Waikato, Department of Computer Science.en_US
dc.identifier.issn1170-487X
dc.identifier.urihttps://hdl.handle.net/10289/1145
dc.description.abstractThe architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable instructions and memory accesses are time stamped. The TimeWarp algorithm is used for managing synchronisation. This algorithm is optimistic and requires that all computations can be rolled back. The basic functions required for implementing the control and memory system used by TimeWarp are described. The memory model presented to the programmer is a single linear address space modified by a single thread of control. Thus, at the software level there is no need for explicit synchronising actions when accessing memory. The physical implementation, however, is multiple CPUs with their own caches and local memory with each CPU simultaneously executing multiple threads of control.en_US
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.relation.ispartofseriesComputer Science Working Papers
dc.subjectcomputer scienceen_US
dc.titleThe architecture of an optimistic CPU: the WarpEngineen_US
dc.typeWorking Paperen_US
uow.relation.series94/16


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