Towards trainable synthesis for optimized circuit deployment on FPGA
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Accepted version, 506.4Kb
Citation
Export citationLegault, J.-P., Patros, P., & Kent, K. B. (2018). Towards trainable synthesis for optimized circuit deployment on FPGA. In Proceedings of 2018 International Symposium on Rapid System Prototyping (RSP) (pp. 90–96). Washington, DC, USA: IEEE. https://doi.org/10.1109/RSP.2018.8631999
Permanent Research Commons link: https://hdl.handle.net/10289/13452
Abstract
Field Programmable Gate Arrays (FPGAs) utilize multiple programmable elements and non-programmable blocks. After synthesizing an input Hardware Design Language (HDL) design into a circuit, optimizations are used to discover a satisfactory deployment on a target FPGA. HDLs' compound operations, such as addition, can be implemented in various ways and thus, multiple but functionally equivalent circuits can be synthesized. To leverage this, we propose a methodology that first enables configurable synthesis of compound operations. Second, it trains the system using a set of HDL files and architectures to optimize target performance objectives, such as critical path length and power. We prototyped our technique in the open source Verilog-To-Routing (VTR) tool. We subsequently produced two configuration files targeting different deployment objectives; experimental results with the VTR Verilog benchmarks revealed significant improvements.
Date
2018Publisher
IEEE
Rights
This is an author’s accepted version of an article published in the Proceedings of 2018 International Symposium on Rapid System Prototyping (RSP). © 2018 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.