Publication: Effects of re-ordered memory operations on parallelism
| dc.contributor.author | Littin, Richard H. | |
| dc.contributor.author | Cleary, John G. | |
| dc.date.accessioned | 2008-10-22T02:58:39Z | |
| dc.date.available | 2008-10-22T02:58:39Z | |
| dc.date.issued | 1997-11 | |
| dc.description.abstract | The performance effect of permitting different memory operations to be re-ordered is examined. The available parallelism is computed using a machine code simulator. A range of possible restrictions on the re-ordering of memory operations is considered: from the purely sequential case where no re-ordering is permitted; to the completely permissive one where memory operations may occur in any order so that the parallelism is restricted only by data dependencies. A general conclusion is drawn that to reliably obtain parallelism beyond 10 instructions per clock will require an ability to re-order all memory instructions. A brief description of a feasible architecture capable of this is given. | en_US |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | Littin, R.H. & Cleary, J.G. (1997). Effects of re-ordered memory operations on parallelism. (Working paper 97/28). Hamilton, New Zealand: University of Waikato, Department of Computer Science. | en_US |
| dc.identifier.issn | 1170-487X | |
| dc.identifier.uri | https://hdl.handle.net/10289/1124 | |
| dc.language.iso | en | |
| dc.publisher | Computer Science, University of Waikato | en_NZ |
| dc.relation.ispartofseries | Computer Science Working Papers | |
| dc.subject | memory access | en_US |
| dc.subject | parallelism | en_US |
| dc.subject | out-of-order execution | en_US |
| dc.title | Effects of re-ordered memory operations on parallelism | en_US |
| dc.type | Working Paper | en_US |
| dspace.entity.type | Publication | |
| pubs.place-of-publication | Hamilton | en_NZ |
| uow.relation.series | 97/28 |